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Preliminary Technical Data
FEATURES
1.5 pF off capacitance 0.5 pC charge injection 33 V supply range 120 on resistance Fully specified at 15 V/+12 V 3 V logic-compatible inputs Rail-to-rail operation Break-before-make switching action 16-lead TSSOP, 20-lead TSSOP, and 4 mm x 4 mm LFCSP Typical power consumption (< 0.03 W)
Low Capacitance, Triple/Quad SPDT 15 V/+12 V iCMOSTM Switches ADG1233/ADG1234
FUNCTIONAL BLOCK DIAGRAMS
ADG1233
S1A D1 S1B S3B D3 S3A S2B D2 S2A S2B D2 S2A S3B D3 S3A S1A D1 S1B
ADG1234
S4A D2 S4B
LOGIC
LOGIC
APPLICATIONS
Audio and video routing Automatic test equipment Data acquisition systems Battery-powered systems Sample-and-hold systems Communication systems
IN1 IN2 IN3 EN
IN1 IN2 IN3 IN4 EN
SWITCHES SHOWN FOR A LOGIC 1 INPUT
Figure 1.
GENERAL DESCRIPTION
The ADG1233 and ADG1234 are monolithic iCMOS analog switches comprising three independently selectable single pole, double throw (SPDT) switches and four independently selectable SPDT switches, respectively. All channels exhibit break-before-make switching action preventing momentary shorting when switching channels. An EN input on the ADG1233 and ADG1234 is used to enable or disable the device. When disabled, all channels are switched off. The iCMOS (industrial-CMOS) modular manufacturing process combines high voltage complementary metal-oxide semiconductor (CMOS) and bipolar technologies. It enables the development of a wide range of high performance analog ICs capable of 33 V operation in a footprint that no other generation of high voltage parts has been able to achieve. Unlike analog ICs using conventional CMOS processes, iCMOS components can tolerate high supply voltages while providing increased performance, dramatically lower power consumption, and reduced package size.
The ultralow capacitance and charge injection of these multiplexers make them ideal solutions for data acquisition and sample-andhold applications, where low glitch and fast settling are required. Fast switching speed coupled with high signal bandwidth make the parts suitable for video signal switching. iCMOS construction ensures ultralow power dissipation, making the parts ideally suited for portable and battery-powered instruments.
PRODUCT HIGHLIGHTS
1. 1.5 pF off capacitance (15 V supply). 2. 0.5 pC charge injection. 3. 3 V logic compatible digital input VIH = 2.0 V, VIL = 0.8 V. 4. 16-lead TSSOP, 20-lead TSSOP, and 4 mm x 4 mm LFCSP.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c) 2005 Analog Devices, Inc. All rights reserved.
05743-001
ADG1233/ADG1234 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagrams............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Dual Supply ................................................................................... 3 Single Supply ................................................................................. 5
Preliminary Technical Data
Absolute Maximum Ratings ............................................................7 ESD Caution...................................................................................7 Pin Configurations and Function Descriptions ............................8 Terminology .................................................................................... 10 Typical Performance Characteristics ........................................... 11 Test Circuits..................................................................................... 14 Outline Dimensions ....................................................................... 16 Ordering Guide .......................................................................... 17
REVISION HISTORY
12/05--Revision PrA: Preliminary Version
Rev. PrA | Page 2 of 20
Preliminary Technical Data SPECIFICATIONS
DUAL SUPPLY1
VDD = +15 V 10%, VSS = -15 V 10%, GND = 0 V, unless otherwise noted. Table 1.
Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Match Between Channels (RON) On Resistance Flatness (RFLAT (ON)) LEAKAGE CURRENTS Source Off Leakage IS (Off ) Drain Off Leakage ID (Off ) Channel On Leakage ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS2 TTRANSITION TBBM tON (EN) tOFF (EN) Charge Injection Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion, THD + N -3 dB Bandwidth CS (Off ) CD (Off ) CD, CS (On) +25C Y Version -40C to +85C -40C to +125C VSS to VDD 120 190 3.5 6 20 60 0.02 0.1 0.02 0.1 0.02 0.1 230 260 Unit V typ max typ max typ max nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max pF typ ns typ ns max ns typ ns min ns typ ns max ns typ ns max pC typ dB typ dB typ % typ MHz typ pF typ pF max pF typ pF max pF typ pF max
Rev. PrA | Page 3 of 20
ADG1233/ADG1234
Test Conditions/Comments
VS = 10 V, IS = -1 mA; see Figure 23 VDD = +13.5 V, VSS = -13.5 V VS = 10 V, IS = -1 mA
10 72
12 79
VS = -5 V, 0 V, +5 V; IS = -1 mA VDD = +16.5 V, VSS = -16.5 V VD = 10 V, VS = -10 V; see Figure 24 VS = 1 V/10 V, VD = 10 V/1 V; see Figure 24 VS = VD = 10 V; see Figure 25
0.6 0.6 0.6
1 1 1 2.0 0.8
0.005 0.1 3 110 130 25 120 140 40 45 0.5 -80 -85 0.14 900 1.5 1.7 1.6 1.8 3.5 4
VIN = VINL or VINH
150
170 10
170 55
195 60
RL = 300 , CL = 35 pF VS = 10 V; see Figure 26 RL = 300 , CL = 35 pF VS1 = VS2 = +10 V; see Figure 27 RL = 300 , CL = 35 pF VS = 10 V; see Figure 28 RL = 300 , CL = 35 pF VS = 10 V; see Figure 28 VS = 0 V, RS = 0 , CL = 1 nF; see Figure 29 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 30 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 32 RL = 10 k, 5 V rms, f = 20 Hz to 20 kHz; see Figure 33 RL = 50 , CL = 5 pF; see Figure 31 f = 1 MHz; VS = 0 V f = 1 MHz; VS = 0 V f = 1 MHz; VS = 0 V f = 1 MHz; VS = 0 V f = 1 MHz; VS = 0 V f = 1 MHz; VS = 0 V
ADG1233/ADG1234
Parameter POWER REQUIREMENTS IDD IDD ISS ISS +25C 0.002 1.0 260 400 0.002 1.0 0.002 1.0
1 2
Preliminary Technical Data
Y Version -40C to +85C -40C to +125C Unit A typ A max A typ A max A typ A max A typ A max Test Conditions/Comments VDD = +16.5 V, VSS = -16.5 V Digital inputs = 0 V or VDD Digital inputs = 5 V Digital inputs = 0 V or VDD Digital inputs = 5 V
Temperature range is Y Version: -40C to +125C. Guaranteed by design, not subject to production test.
Rev. PrA | Page 4 of 20
Preliminary Technical Data
SINGLE SUPPLY1
VDD = 12 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 2.
Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Match Between Channels (RON) On Resistance Flatness (RFLAT (ON)) LEAKAGE CURRENTS Source Off Leakage IS (Off ) Drain Off Leakage ID (Off ) Channel On Leakage ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS2 TTRANSITION TBBM tON (EN) tOFF (EN) Charge Injection Off Isolation Channel-to-Channel Crosstalk -3 dB Bandwidth CS (Off ) CD (Off ) CD, CS (On) +25C Y Version -40C to +85C -40C to +125C 0 to VDD 300 475 5 16 60 0.02 0.1 0.02 0.1 0.02 0.1 567 625 Unit V typ max typ max typ nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max pF typ ns typ 200 230 10 150 195 45 60 -0.3 -80 -85 600 1.5 1.7 2 2.2 4 4.5 230 70 265 ns typ 75 pC typ dB typ dB typ MHz typ pF typ pF max pF typ pF max pF typ pF max ns typ ns min ns typ
ADG1233/ADG1234
Test Conditions/Comments
VS = 0 V to10 V, IS = -1 mA; see Figure 23 VDD = 10.8 V, VSS = 0 V VS = 0 V to10 V, IS = -1 mA
26
27
VS = 3 V, 6 V, 9 V, IS = -1 mA VDD = 13.2 V VS = 1 V/10 V, VD = 10 V/1 V; see Figure 24 VS = 1 V/10 V, VD = 10 V/1 V; see Figure 24 VS = VD = 1 V or 10 V, see Figure 25
0.6 0.6 0.6
1 1 1 2.0 0.8
0.001 0.1 2 135 170 45
VIN = VINL or VINH
RL = 300 , CL = 35 pF VS = 8 V; see Figure 26 RL = 300 , CL = 35 pF VS1 = VS2 = 8 V; see Figure 27 RL = 300 , CL = 35 pF VS = 8 V; see Figure 28 RL = 300 , CL = 35 pF VS = 8 V; see Figure 28 VS = 6 V, RS = 0 , CL = 1 nF; see Figure 29 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 30; RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 32 RL = 50 , CL = 5 pF; see Figure 31 f = 1 MHz; VS = 6 V f = 1 MHz; VS = 6 V f = 1 MHz; VS = 6 V f = 1 MHz; VS = 6 V f = 1 MHz; VS = 6 V f = 1 MHz; VS = 6 V
Rev. PrA | Page 5 of 20
ADG1233/ADG1234
Parameter POWER REQUIREMENTS IDD IDD +25C 0.002 1.0 260 420
1 2
Preliminary Technical Data
Y Version -40C to +85C -40C to +125C Unit A typ A max A typ A max Test Conditions/Comments VDD = 13.2 V Digital inputs = 0 V or VDD Digital inputs = 5 V
Temperature range is Y Version: -40C to +125C Guaranteed by design, not subject to production test.
Rev. PrA | Page 6 of 20
Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 3.
Parameter VDD to VSS VDD to GND VSS to GND Analog, Digital Inputs1 Rating 35 V -0.3 V to +25 V +0.3 V to -25 V VSS - 0.6 V to VDD + 0.6 V or 100 mA, whichever occurs first 24 mA 100 mA
ADG1233/ADG1234
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time.
Continuous Current, S or D Peak Current, S or D (Pulsed at 1 ms, 10% Duty Cycle max) Operating Temperature Range Automotive Temperature Range (Y Version) Storage Temperature Range Junction Temperature TSSOP, JA, Thermal Impedance LFCSP, JA, Thermal Impedance Reflow Soldering Peak Temperature, Pb-free
1
-40C to +125C -65C to +150C 150C 112C/W 30.4C/W 260C
Overvoltages at A, EN, S, or D are clamped by internal diodes. Current should be limited to the maximum ratings given.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. PrA | Page 7 of 20
ADG1233/ADG1234 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Preliminary Technical Data
16 S1A 14 GND
15 VDD
VDD S1A D1 S1B S2B D2 S2A IN2
1 2 3 4 5 6 7 8
16 15
GND IN1 EN VSS S3B D3 S3A
05743-002
ADG1233
TOP VIEW (Not to Scale)
14 13 12 11 10 9
D1 1 S1B 2 S2B 3 D2 4
PIN 1 INDICATOR
13 IN1
12 EN 11 VSS 10 S3B 9 D3
ADG1233
TOP VIEW (Not to Scale)
S2A 5
S3A 8
IN2 6
IN3 7
IN3
Figure 2. 16-Lead TSSOP Pin Configuration
Figure 4. 16-Lead, 4 mm x 4 mm LFCSP Pin Configuration, Exposed Pad Tied to Substrate, VSS
S1A IN1 EN IN4 S4A
IN1 1 S1A 2 D1 3 S1B
4
20 19
IN4 S4A D4 S4B VDD EN S3B
ADG1234
TOP VIEW (Not to Scale)
18 17 16 15 14 13 12 11
VSS 5 GND S2B
6 7
D1 S1B VSS GND S2B
1 2 3 4 5
20 19 18 17 16
PIN 1 INDICATOR
ADG1234
TOP VIEW (Not to Scale)
15 D4 14 S4B 13 VDD 12 S3B 11 D3
D2 6 S2A 7 IN2 8 IN3 9 S3A 10
05743-004
D2 8 S2A 9 IN2 10
D3
05743-003
S3A IN3
Figure 3. 20-Lead TSSOP Pin Configuration
Figure 5. 20-Lead, 4 mm x 4 mm LFCSP Pin Configuration Exposed Pad Tied to Substrate, VSS
Table 4. 16-Lead TSSOP/20-Lead TSSOP Pin Configurations
Pin No. ADG1233-- 16-Lead TSSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 N/A N/A N/A N/A Pin No. ADG1234-- 20-Lead TSSOP 16 2 3 4 7 8 9 10 11 12 13 14 5 15 1 6 17 18 19 20 Mnemonic VDD S1A D1 S1B S2B D2 S2A IN2 IN3 S3A D3 S3B VSS EN IN1 GND S4B D4 S4A IN4
Table 5. 16-Lead LFCSP/20-Lead LFCSP Pin Configurations
Pin No. ADG1233-- 16-Lead LFCSP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 N/A N/A N/A N/A Pin No. ADG1234-- 20-Lead LFCSP 1 2 5 6 7 8 9 10 11 12 3 18 19 4 13 20 14 15 16 17 Mnemonic D1 S1B S2B D2 S2A IN2 IN3 S3A D3 S3B VSS EN IN1 GND VDD S1A S4B D4 S4A IN4
Rev. PrA | Page 8 of 20
05743-005
Preliminary Technical Data
Table 6. ADG1233/ADG1234 Truth Table
EN 1 0 0 INx X 0 1 Switch xA Off Off On Switch xB Off On Off
ADG1233/ADG1234
Rev. PrA | Page 9 of 20
ADG1233/ADG1234 TERMINOLOGY
VDD Most positive supply potential. VSS Most negative power supply potential in dual supplies. In single-supply applications, it can be connected to ground. GND Ground (0 V) reference. RON Ohmic resistance between D and S. RON Difference between the RON of any two channels. IS (Off) Source leakage current when switch is off. ID (Off) Drain leakage current when switch is off. ID, IS (On) Channel leakage current when switch is on. VD (VS) Analog voltage on Terminal D, Terminal S. CS (OFF) Channel input capacitance for off condition. CD (Off) Channel output capacitance for off condition. CD, CS (On) On switch capacitance. CIN Digital input capacitance. tON (EN) Delay time between the 50% and 90% points of the digital input and switch on condition.
Preliminary Technical Data
tOFF (EN) Delay time between the 50% and 90% points of the digital input and switch off condition. tTRANSITION Delay time between the 50% and 90% points of the digital inputs and the switch on condition when switching from one address state to another. TBBM Off time measured between the 80% point of both switches when switching from one address state to another. VINL Maximum input voltage for Logic 0. VINH Minimum input voltage for Logic 1. IINL (IINH) Input current of the digital input. IDD Positive supply current. ISS Negative supply current. Off Isolation A measure of unwanted signal coupling through an off channel. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. Bandwidth Frequency at which the output is attenuated by 3 dB. On Response Frequency response of the on switch. THD + N Ratio of the harmonic amplitude plus noise of the signal to the fundamental.
Rev. PrA | Page 10 of 20
Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS
200 180 160 TA = 25C VDD = 13.5V VSS = -13.5V VDD = 15V VSS = -15V 200 250
ADG1233/ADG1234
VDD = 15V VSS = -15V
ON RESISTANCE ()
ON RESISTANCE ()
140 120 100 80 60 40
05743-031
TA = +125C 150 TA = +85C TA = +25C 100 TA = -40C 50
05743-034
VDD = 16.5V VSS = -16.5V
20 0 -18 -15 -12 -9 -6 -3 0 3 6 9 SOURCE OR DRAIN VOLTAGE (V) 12 15 18
0 -15
-10
-5 0 5 TEMPERATURE (C)
10
15
Figure 6. On Resistance as a Function of VD (VS ) for Dual Supply
Figure 9. On Resistance as a Function of VD (VS ) for Different Temperatures, Dual Supply
600 VDD = 12V VSS = 0V
600 TA = 25C 500 VDD = 4.5V VSS = -4.5V
TA = +125C 500
ON RESISTANCE ()
ON RESISTANCE ()
VDD = 5V VSS = -5V 400
TA = +85C 400 TA = +25C 300
300
VDD = 5.5V VSS = -5.5V
200
200
TA = -40C
100
05743-032
100
05743-035
0 -6
0 0 2 4 6 8 TEMPERATURE (C) 10 12
-4
-2 0 2 SOURCE OR DRAIN VOLTAGE (V)
4
6
Figure 7. On Resistance as a Function of VD (VS ) for Dual Supply
450 TA = 25C 400 350 VDD = 10.8V VSS = 0V VDD = 12V VSS = 0V
Figure 10. On Resistance as a Function of VD (VS ) for Different Temperatures, Single Supply
400 300 200 VDD = +15V VSS = -15V VBIAS = +10V/-10V ID, IS (ON)
ON RESISTANCE ()
LEAKAGE (pA)
300 250 200 150 100 50 0 0 2 4 6 8 10 SOURCE OR DRAIN VOLTAGE (V) 12 14
05743-033
100 IS, ID (OFF) 0 -100 IS, ID (OFF) -200 -300 -400 0 20 40 60 80 TEMPERATURE (C) 100 120 ID, IS (ON)
05743-017
VDD = 13.2V VSS = 0V
Figure 8. On Resistance as a Function of VD (VS ) for Single Supply
Figure 11. Leakage Currents as a Function of Temperature, Dual Supply
Rev. PrA | Page 11 of 20
ADG1233/ADG1234
200 150 100 VDD = 12V VSS = 0V VBIAS = 1V/10V ID (OFF) ID, IS (ON)
Preliminary Technical Data
220 200 180 160 140
IS (OFF)
AOFF BON 12V DS
AOFF BON 15V DS
LEAKAGE (pA)
50
TIME (ns)
120 100 80
0 -50 ID, IS (ON) -100 ID (OFF)
05743-018
60 40 20 0 -40 -20 0 BOFF AON 12V DS
BOFF AON 15V DS
-200 0 20 40 60 80 TEMPERATURE (C) 100 120
20 40 60 TEMPERATURE (C)
80
100
120
Figure 12. Leakage Currents as a Function of Temperature, Single Supply
200 180 160 140 IDD PER CHANNEL TA = +25C
Figure 15. TTRANSITION vs. Temperature
0 -10 -20 OFF ISOLATION (dB) -30 -40 -50 -60 -70 -80 -90 VDD = +15V VSS = -15V TA = +25C
VDD = +15V VSS = -15V
IDD (A)
120 100 80 60 40 20 0 0 2 4 6 8 10 LOGIC, INX (V) 12 14 VDD = +12V VSS = 0V
05743-006
-100 -110 10k 100k 1M 10M FREQUENCY (Hz) 100M
16
1G
Figure 13. IDD vs. Logic Level
6 TA = +25C 4 -30
CHARGE INJECTION (pC) CROSSTALK (dB)
Figure 16. Off Isolation vs. Frequency
-10 VDD = +15V VSS = -15V -20 VDD = +15V VSS = -15V TA = +25C
2
VDD = +5V VSS = -5V
-40 -50 -60 -70 -80 SxA - SxB
0
VDD = +12V VSS = 0V
-2
S1x - S2x
-4
05743-008
-90 -100 10k 100k 1M 10M FREQUENCY (Hz) 100M
-6 -15
-10
-5
0 VS (V)
5
10
15
1G
Figure 14. Charge Injection vs. Source Voltage
Figure 17. Crosstalk vs. Frequency
Rev. PrA | Page 12 of 20
05743-012
05743-036
05743-011
-150
Preliminary Technical Data
0 VDD = +15V VSS = -15V TA = +25C -5
ON RESPONSE (dB) CAPACITANCE (pF)
ADG1233/ADG1234
5.0 4.5 4.0 3.5 3.0 2.5 DRAIN OFF 2.0 1.5 SOURCE OFF 1.0
05743-013
VDD = 12V VSS = 0V TA = 25C SOURCE/DRAIN ON
-10
-15
-20
0.5 0 0 2 4 5 VBIAS (V) 8 10
-25 10k
100k
1M
10M 100M FREQUENCY (Hz)
1G
10G
12
Figure 18. On Response vs. Frequency
10.00 LOAD = +10k TA = +25C
Figure 21. Capacitance vs. Source Voltage for Single Supply
5.0 4.5 4.0 SOURCE/DRAIN ON VDD = +5V VSS = -5V TA = +25C
1.00
THD+N (%)
VDD = +5V, VSS = -5V, VS = +3.5Vrms
CAPACITANCE (pF)
3.5 3.0 2.5 2.0 1.5 1.0 SOURCE OFF DRAIN OFF
VDD = +15V, VSS = -15V, VS = +5Vrms 0.10
05743-037
0.5 0 -5 -4 -3 -2 -1 0 1 VBIAS (V) 2 3 4 5
0.01 10
100
1k FREQUENCY (Hz)
10k
100k
Figure 19. THD + N vs. Frequency
5.0 4.5 4.0
CAPACITANCE (pF)
Figure 22. Capacitance vs. Source Voltage for Dual Supply
VDD = +15V VSS = -15V TA = +25C
3.5 3.0 2.5
SOURCE/DRAIN ON
DRAIN OFF 2.0 1.5 SOURCE OFF 1.0 0.5 0 -15 -10 -5 0 VBIAS (V) 5 10
05743-010
15
Figure 20. Capacitance vs. Source Voltage for Dual Supply
Rev. PrA | Page 13 of 20
05743-007
05743-009
ADG1233/ADG1234 TEST CIRCUITS
V
Preliminary Technical Data
ID (ON)
S D IDS VS
05743-020
NC
S
D
A VD
05743-022
NC = NO CONNECT
Figure 23. On Resistance
IS (OFF) A VS S D ID (OFF) A VD
05743-021
Figure 25. On Leakage
Figure 24. Off Leakage
0.1F
VDD
VSS
0.1F
VIN
50%
50%
VDD VS SxB SxA INx VIN GND
VSS D RL 300 CL 35pF VOUT VIN 50% 90% 50% 90%
VOUT
tON
tOFF
Figure 26. Switching Timing
0.1F
VDD
VSS
0.1F VIN
VDD VS SxB SxA INx VIN GND
VSS D RL 300 CL 35pF VOUT
VOUT
80%
tBBM
tBBM
05743-024
Figure 27. Break-Before-Make Delay
Rev. PrA | Page 14 of 20
05743-023
Preliminary Technical Data
0.1F VDD VSS 0.1F 3V VDD IN3 IN2 IN1 EN VIN 50 GND VSS S1A S1B VS ENABLE DRIVE (VIN) 0V 50% 50%
ADG1233/ADG1234
ADG1233
D1 RL 300 VO CL 35pF
tOFF(EN)
VO OUTPUT 0V 0.9V0 0.9V0
05743-025
tON(EN)
Figure 28. Enable Delay, tON (EN), tOFF (EN)
0.1F
VDD
VSS
0.1F VIN (NORMALLY CLOSED SWITCH) ON NC VOUT CL 1nF VIN (NORMALLY OPEN SWITCH) VOUT VOUT OFF
VDD D
VSS SxB
VS
SxA INx VIN GND
Figure 29. Charge Injection
VDD 0.1F
VSS 0.1F NETWORK ANALYZER NC 50
VDD 0.1F
05743-026
QINJ = CL x VOUT
VSS 0.1F
VDD
VSS
NETWORK ANALYZER VOUT RL 50
VDD SxA
VSS
INx
SxA
D
SxB
50 VS VOUT
SxB INx VS GND
D
R 50
VIN GND
RL 50
OFF ISOLATION = 20 log
VS
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
VOUT VS
Figure 30. Off Isolation
VDD 0.1F VSS 0.1F NETWORK ANALYZER NC INx SxA SxB VS
INx VDD 0.1F
Figure 32. Channel-to-Channel Crosstalk
VSS 0.1F AUDIO PRECISION VDD S VS V p-p RL 10 GND
05743-028
VDD
VSS
VSS RS
50
D
VIN GND RL 50 VOUT
VIN
D VOUT
05743-029
05743-030
VOUT
INSERTION LOSS = 20 log
VOUT WITH SWITCH VOUT WITHOUT SWITCH
05743-027
Figure 31. Bandwidth
Figure 33. THD + Noise
Rev. PrA | Page 15 of 20
ADG1233/ADG1234 OUTLINE DIMENSIONS
5.10 5.00 4.90
Preliminary Technical Data
6.60 6.50 6.40
9
20 11
16
4.50 4.40 4.30
1 8
6.40 BSC
4.50 4.40 4.30 6.40 BSC
1 10
PIN 1 1.20 MAX 0.20 0.09 0.65 BSC 0.30 0.19 COPLANARITY 0.10 SEATING PLANE 8 0 0.75 0.60 0.45
PIN 1 0.65 BSC 0.15 0.05 COPLANARITY 0.10 0.30 0.19 1.20 MAX 0.20 0.09 8 0 0.75 0.60 0.45
0.15 0.05
SEATING PLANE
COMPLIANT TO JEDEC STANDARDS MO-153-AC
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 34. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters
Figure 35. 20-Lead Thin Shrink Small Outline Package [TSSOP] (RU-20) Dimensions shown in millimeters
4.00 BSC SQ
0.60 MAX 0.60 MAX
13 12 16 1
PIN 1 INDICATOR 2.25 2.10 SQ 1.95 0.25 MIN 1.95 BSC
PIN 1 INDICATOR
TOP VIEW
0.65 BSC 3.75 BSC SQ 0.75 0.60 0.50
EXPOSED PAD
(BOTTOM VIEW)
9 8 5
4
12 MAX 1.00 0.85 0.80
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM
SEATING PLANE
0.30 0.23 0.18
0.20 REF
COPLANARITY 0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VGGC
Figure 36. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm x 4 mm Body, Very Thin Quad (CP-16-4) Dimensions shown in millimeters
Rev. PrA | Page 16 of 20
Preliminary Technical Data
0.60 MAX 0.60 MAX PIN 1 INDICATOR TOP VIEW 3.75 BCS SQ 0.75 0.55 0.35 12 MAX 1.00 0.85 0.80 SEATING 0.50 PLANE BSC 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.20 REF COPLANARITY 0.08
11 10 6 5
ADG1233/ADG1234
4.00 BSC SQ
PIN 1 INDICATOR
20 1
16 15
2.25 2.10 SQ 1.95 0.25 MIN 0.30 0.23 0.18
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1
Figure 37. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm x 4 mm Body, Very Thin Quad (CP-20-1) Dimensions shown in millimeters
ORDERING GUIDE
Model ADG1233YRUZ1 ADG1233YRUZ-REEL71 ADG1233YCPZ-REEL1 ADG1233YCPZ-REEL71 ADG1234YRUZ1 ADG1234YRUZ-REEL71 ADG1234YCPZ-REEL1 ADG1234YCPZ-REEL71
1
Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C
Description 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 16-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 20-Lead Thin Shrink Small Outline Package (TSSOP) 20-Lead Thin Shrink Small Outline Package (TSSOP) 20-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 20-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
Package Option RU-16 RU-16 CP-16-4 CP-16-4 RU-20 RU-20 CP-20-1 CP-20-1
Z = Pb-free part.
Rev. PrA | Page 17 of 20
ADG1233/ADG1234 NOTES
Preliminary Technical Data
Rev. PrA | Page 18 of 20
Preliminary Technical Data NOTES
ADG1233/ADG1234
Rev. PrA | Page 19 of 20
ADG1233/ADG1234 NOTES
Preliminary Technical Data
(c) 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR05743-0-12/05(PrA)
Rev. PrA | Page 20 of 20

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